1. Field of the Invention
The present invention relates to phase frequency detectors and, more particularly, to a fractional-rate phase frequency detector.
2. Description of the Related Art
A serial data receiver is a device that receives a serial data bit stream, and converts the data in the steam into a format which can be processed. To extract the data from the serial data bit stream, a serial data receiver must typically recover the clock signal that was used to clock the serial data bit stream from the serial data bit stream.
To recover the clock signal from a serial data bit stream, serial data receivers commonly utilize a circuit known as a phase-locked-loop (PLL). A conventional PLL includes a voltage-controlled oscillator (VCO), a phase frequency detector that is connected to the VCO, and a loop filter that is connected to the phase frequency detector and the VCO.
In operation, the VCO generates a recovered clock signal that has a phase and frequency which are defined by the value of a VCO control voltage. In addition, the phase frequency detector detects the difference in phase and frequency between the edges of the recovered clock signal and the edges within the serial data bit stream.
The loop filter filters the phase and frequency differences to output the VCO control voltage to the VCO to adjust the phase and frequency of the recovered clock signal until the phase and frequency of the recovered clock signal match the phase and frequency of the clock signal that was used to clock the serial data bit stream.
Thus, when the recovered clock signal locks onto the edges in the serial data bit stream, the recovered clock signal is substantially the same as the clock signal used to clock the serial data bit stream. As a result, the phase and frequency of the recovered clock signal and the phase and frequency of the clock signal used to clock the serial data bit steam are substantially the same.
There are many types of phase frequency detectors known in the art. One type of phase frequency detector is a Pottbacker phase frequency detector. Pottbacker phase frequency detectors are always connected to a VCO circuit that outputs the recovered clock signal as an in-phase clock signal, and also outputs a quadrature clock signal (a clock signal that is identical to the in-phase clock signal, but which lags the in-phase clock signal by 90°).
FIG. 1 shows a diagram that illustrates a prior-art Pottbacker phase frequency detector 100. As shown in FIG. 1, Pottbacker phase frequency detector 100 includes a phase detector 110 that detects a difference in phase between the edges of an in-phase clock signal CLK-I and the edges in a serial data bit steam DBS, which are clocked by a clock signal, and generates a phase difference signal PD that represents the difference in phase.
As further shown in FIG. 1, phase detector 110 is implemented with a conventional D flip flop 112 that has a data input D connected to receive the in-phase clock signal CLK-I, a clock input connected to receive the serial data bit stream DBS, and a Q output that generates the phase difference signal PD. The serial data bit stream DBS can be, for example, in a non-return to zero (NRZ) format.
FIGS. 2A-2B show diagrams that illustrate the operation of phase detector 110. FIG. 2A shows the in-phase clock signal CLK-I, while FIG. 2B shows the Q output Q112 of flip flop 112. As shown in FIGS. 2A-2B, if an edge in the serial data bit stream DBS (which corresponds with an edge of the clock signal used to clock the serial data bit stream DBS) clocks flip flop 112 when the in-phase clock signal CLK-I is low, flip flop 112 outputs the phase difference signal PD with a logic zero. Similarly, if the edge clocks flip flop 112 when the in-phase clock signal CLK-I is high, flip flop 112 outputs the phase difference signal PD with a logic high.
Referring again to FIG. 1, Pottbacker phase frequency detector 100 also includes a phase detector 120 that detects a difference in phase between the edges of an out-of-phase clock signal CLK-Q and the edges in the serial data bit steam DBS, and generates a phase difference signal OD that represents the difference in phase. The out-of-phase clock signal CLK-Q is the same as the in-phase clock signal CLK-I, but lags the in-phase clock signal CLK-I by 90°.
As shown in FIG. 1, phase detector 120 is implemented with a conventional D flip flop 122 that has a data input D connected to receive the out-of-phase clock signal CLK-Q, a clock input connected to receive the serial data bit stream DBS, and a Q output that generates the phase difference signal OD.
FIGS. 3A-3B show diagrams that illustrate the operation of phase detector 120. FIG. 3A shows the out-of-phase clock signal CLK-Q, while FIG. 3B shows the Q output Q122 of flip flop 122. As shown in FIGS. 3A-3B, the logic state output by the Q output Q112 of flip flop 122 depends on when an edge in the serial data bit stream DBS (which corresponds with an edge of the clock signal used to clock the serial data bit stream DBS) clocks flip flop 122.
Referring again to FIG. 1, Pottbacker phase frequency detector 100 further includes a frequency detector 130 that detects a difference in frequency between the in-phase clock signal CLK-I and the clock signal used to clock the serial data bit steam DBS as represented by the edges in the serial data bit stream DBS, and generates a frequency difference signal FD that represents the difference in frequency.
As shown in FIG. 1, frequency detector 130 is implemented with a conventional D flip flop 132 that has a data input D connected to the Q output of flip flop 122 to receive the phase difference signal OD, a clock input connected to the Q output of flip flop 112 to receive the phase difference signal PD, and a Q output that generates the frequency difference signal FD.
One of the drawbacks of Pottbacker phase frequency detector 100 is that as the frequencies of the serial data bit streams reach ever higher rates, it becomes increasingly harder to route the in-phase clock signal CLK-I (i.e., the recovered clock signal) around to each of the devices that are clocked by the in-phase clock signal CLK-I.
For example, when the serial data bit stream DBS was clocked at a frequency of 12.5 GHz, the VCO locks and generates a 12.5 GHz in-phase clock signal CLK-I, which is routed to the other clocked devices. However, when the clock signal used to clock the serial data bit stream reaches a frequency of, for example, 25 GHz, it becomes increasingly difficult to route a 25 GHz in-phase clock signal around to the other clocked elements.